1. Field of the Invention
The invention relates to the output interfaces of integrated circuits for driving data buses. More particularly, the invention relates, in a nonlimiting manner, to a universal serial bus (USB) driver circuit.
2. Description of the Related Art
The trend in the development of communication buses is towards incessantly increasing the data transmission speeds in electronic systems. Moreover, the integration of the electronic circuits entails miniaturizing and implementing in integrated circuit form the circuits directly driving the communication buses. A typical example of communication bus operating at high speed is known by the name of Universal Serial Bus (defined by the USB standard). USBs are commonly used to enable personal computers, typically of PC type, to communicate with external peripheral devices. The external peripheral devices are, for example, portable music players, removable storage drives, digital photographic devices, modems, and even peripheral devices incorporating a number of functions such as mobile telephones. In the current version of the standard, USB 2.0, the nominal data rate is equal to 12 Megabits per second but a maximum transmission speed of up to 480 Megabits per second is allowed. To achieve such data rates, there are a relatively large number of constraints on the circuits.
An exemplary output interface, designed to drive a USB bus, is represented in FIG. 1. The USB bus comprises a differential data bus comprising two conductor wires 1 and 2 each driven by a driver circuit 100A and 200A. The bus is a differential bus, which improves the signal-to-noise ratio. The input signals of the two driver circuits 100A and 200A are mutually inverted so that the outputs of said circuits 100A and 200A are complementary. The driver circuits 100A and 200A are often currently made of CMOS technology, but can also use bipolar transistors.
Each driver circuit 100A comprises a pair of transistors 101 and 102 of opposing types, that is, one PMOS and one NMOS, the conduction channels of which are linked in series between two power supply conductors respectively supporting a high power supply voltage V+ and a low power supply voltage V−. To limit the consumption of this pair of transistors 101 and 102 when they switch, these transistors are driven separately so that one begins to conduct only when the other stops conducting. To stagger the switching of the two transistors in time, two control circuits 103 and 104, respectively linked to the gates of the transistors 101 and 102, supply said gates with voltages, the increasing or the decreasing of which is controlled to obtain different slopes on a transition of a control signal CS intended to be sent over the differential bus comprising wires 1 and 2.
Each control circuit 103, or 104, comprises a controlled current source 105, or 106, and a capacitor 107, or 108, to supply a voltage ramp in response to a transition of the signal CS. Thus, on a transition of the signal CS, each current source 105, or 106, is switched to supply a constant current to charge or discharge the capacitor 107, or 108, as well as the equivalent capacitance of the gate of the transistor 101, or 102, controlled by said source 105, or 106. The slope is controlled by assigning a current value that is higher in absolute terms to discharge the gate of the transistor for which conduction is to be stopped. The capacitors 107 and 108 are, furthermore, linked to the output of the driver circuit 100A in order also to control the transition slope of the output of the driver circuit 100A. The gate-source voltage of the transistor 101 or 102 is held constant when the latter reaches a balance voltage while the conductor wire 1 is charging or discharging. This balance is created automatically when the gate-source voltage of the transistor 101 or 102, switched to become conducting, enables said transistor 101 or 102 to supply a current equal to IC+IS such that |IC/C1|=|IS/CL|, with IC being the current supplied by the source 105 or 106, to switch on the transistor 101 or 102, C1 being the capacitance of the capacitor 107 or 108, Is being the output current supplied by the driver circuit and CL being the capacitance of the conductor wire 1. The capacitor 107 or 108 and the current IC are dimensioned according to the switching slope required on the bus, taking into account the specifications of the USB standard.
A problem with this known interface is that, because of the spread of component characteristics, it presents switching synchronization defects between the driver circuits 100A and 200A. These synchronization defects become more problematic as the frequency increases. One solution for making the operation of the two circuits uniform is disclosed in EP-A-1 291 780. The outputs of each driver circuit are linked to the gates of the other driver circuit by capacitive coupling. The solution developed in this patent application gives good results but has the effect of delaying the fastest circuit to the detriment of the overall speed of the interface comprising the two circuits.